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K6F1008V2M, K6F1008S2M, K6F1008R2M Family
Document Title
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 0.1 Initial draft Revise - Erase 100ns from KM68FS1000 Family - Add 150ns for KM68FS1000 Family - Add 32-sTSOP1 new package - Add high power version ISB1=5.0A(Max) - Change VDR(Min) 1.0 to 1.5V Finalize - Concept change high power version to low low power version ISB1=5.0A(Max) - Change super low power version with special handling ISB1=1.0A(Max) - Icc & Icc1(Read) decrease 10 to 5mA Revise - Change datasheet format - Remove reverse type package from product - Remove reserved speed bin(100ns) Revise - Add CSP type packaged product. - Improved ICC2
Draft Date
March 15, 1996 July 7, 1996
Remark
Advance Preliminary
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1.0
December 1, 1996
Final
2.0
February 26, 1998
Final
3.0
July 29, 1998
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
CMOS SRAM
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
* Process Technology: Full CMOS * Organization: 128K x8 bit * Power Supply Voltage K6F1008V2M Family: 3.0V ~ 3.6V K6F1008S2M Family: 2.3V ~ 3.3V K6F1008R2M Family: 1.8V ~ 2.7V * Low Data Retention Voltage: 1.5V(Min) * Three state output and TTL Compatible * Package Type: 32-SOP-525, 32-TSOP1-0820F, 32-TSOP1-0813.4F, 48-CSP
GENERAL DESCRIPTION
The K6F1008V2M, K6F1008S2M and K6F1008R2M families are fabricated by SAMSUNGs advanced Full CMOS process technology. The families support various operating temperature range and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
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PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range K6F1008V2M-C K6F1008S2M-C K6F1008R2M-C K6F1008V2M-I K6F1008S2M-I K6F1008R2M-I Industrial(-40~85C) Commercial(0~70C) 3.0~3.6V 2.3~3.3V 1.8~2.7V 3.0~3.6V 2.3~3.3V 1.8~2.7V Speed(ns) Standby (ISB1, Max) Operating (ICC2, Max) 40mA 35mA 30mA 5A2) 15mA 40mA 35mA 30mA 15mA 32-SOP 32-TSOP1 Forward 32-sTSOP1 Forward 48-CSP PKG Type
701)/85@VCC=3.30.3V 70 /85@VCC=3.00.3V 1201)/150@VCC=2.50.2V 300 @VCC=2.00.2V 701)/85@VCC=3.30.3V 70 /85/100@VCC=3.00.3V 1201)/150@VCC=2.50.2V 300 @VCC=2.00.2V
1) 1) 1) 1)
1. The parameter is measured with 30pF test load. 2. 1A for super low power version with special handling.
PIN DESCRIPTION
N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 C D E F G H A B A11 A9 A8 A13 WE CS2 A15 VCC N.C A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 6 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
A8 A13 A15 A16 A7 A6 A5 A4 A14 A12
32-TSOP 32-sTSOP Type1-Forward
32-SOP
Row select
Memory array 1024 rows 128x8 columns
2
3
4
5
A0 I/O5 I/O6 VSS VCC I/O7 I/O8 A9
A1 A2
CS2 WE NC
A3 A4 A5
A6 A7
A8 I/O1
I/O1
I/O2 VCC VSS
I/O8
Data cont Data cont
A10 A0
I/O Circuit Column select
NC OE A10 CS1 A11
NC A16 A12 A15 A13
I/O3 I/O4 A14
CS1 CS2 WE OE
A1
A2
A3 A9
A11
48-CSP - TOP VIEW
Control logic
Name
Function
Name OE WE
Function Output Enable Input Write Enable Input
Name Vcc Vss
Function Power Ground
Name
Function
CS1,CS2 Chip Select Input N.C. No Connection
I/O1~I/O8 Data Inputs/Outputs A0~A16 Address Inputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PRODUCT LIST
Commercial Temperature Products(0~70C) Part Name K6F1008V2M-GC70 K6F1008V2M-GC85 K6F1008V2M-TC70 K6F1008V2M-TC85 K6F1008S2M-GC12 K6F1008S2M-GC15 K6F1008S2M-TC12 K6F1008S2M-TC15 K6F1008S2M-YC12 www..com K6F1008S2M-YC15 Function 32-SOP, 70ns, 3.3V 32-SOP, 85ns, 3.3V 32-TSOP1 F, 70ns, 3.3V 32-TSOP1 F, 85ns, 3.3V 32-SOP, 120/70ns, 2.5/3.0V 32-SOP, 150/85ns, 2.5/3.0V 32-TSOP1 F, 120/70ns, 2.5/3.0V 32-TSOP1 F, 150/85ns, 2.5/3.0V 32-sTSOP1 F, 120/70ns, 2.5/3.0V 32-sTSOP1 F, 150/85ns, 2.5/3.0V
CMOS SRAM
Industrial Temperature Products(-40~85C) Part Name K6F1008V2M-GI70 K6F1008V2M-GI85 K6F1008V2M-TI70 K6F1008V2M-TI85 K6F1008S2M-GI12 K6F1008S2M-GI15 K6F1008S2M-TI12 K6F1008S2M-TI15 K6F1008S2M-YI12 K6F1008S2M-YI15 K6F1008S2M-ZI15 K6F1008R2M-GI30 K6F1008R2M-TI30 K6F1008R2M-YI30 K6F1008R2M-ZI30 Function 32-SOP, 70ns, 3.3V 32-SOP, 85ns, 3.3V 32-TSOP1 F, 70ns, 3.3V 32-TSOP1 F, 85ns, 3.3V 32-SOP, 120/70ns, 2.5/3.0V 32-SOP, 150/85ns, 2.5/3.0V 32-TSOP1 F, 120/70ns, 2.5/3.0V 32-TSOP1 F, 150/85ns, 2.5/3.0V 32-sTSOP1 F, 120/70ns, 2.5/3.0V 32-sTSOP1 F, 150/85ns, 2.5/3.0V 48-CSP, 150/100ns, 2.5/3.0V 32-SOP, 300ns, 2.0/2.5V 32-TSOP1 F, 300ns, 2.0/2.5V 32-sTSOP1 F, 300ns, 2.0/2.5V 48-CSP, 300ns, 2.0/2.5V
K6F1008R2M-GC30 K6F1008R2M-TC30 K6F1008R2M-YC30
32-SOP, 300ns, 2.0/2.5V 32-TSOP1 F, 300ns, 2.0/2.5V 32-sTSOP1 F, 300ns, 2.0/2.5V
FUNCTIONAL DESCRIPTION
CS1 H X1) L L L CS2 X1) L H H H OE X1) X1) H L X
1)
WE X1) X1) H H L
I/O High-Z High-Z High-Z Dout Din
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
1. X means dont care. (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN,VOUT VCC PD TSTG TA -40 to 85 TSOLDER 260C, 5sec (Lead Only) Ratings -0.2 to 3.6V2) -0.2 to 4.0V 1.0 -55 to 150 0 to 70
3)
Unit V V W C
Remark -
C K6F1008V2M-C, K6F1008S2M-C, K6F1008R2M-C C K6F1008V2M-I, K6F1008S2M-I, K6F1008R2M-I -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN/VOUT=-0.2 to 3.9V for K6F1008V2M Family. 3. Maximum VCC=-0.2 to 4.6V for K6F1008V2M Family.
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Symbol Product
K6F1008V2M Family
CMOS SRAM
Min 3.0 2.3 1.8 0 Vcc=3.30.3V Vcc=3.00.3V Vcc=2.50.2V 2.2 2.2 2.0 2.0 1.6 -0.23)
Typ 3.3 2.5/3.0 2.0/2.5 0
Max 3.6 3.3 2.7 0
Unit
Supply voltage
Vcc
K6F1008S2M Family K6F1008R2M Family
V
Ground
Vss
All Family
K6F1008V2M Family K6F1008S2M Family
V
Input high voltage
VIH
-
Vcc+0.22)
V
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Input low voltage VIL
K6F1008R2M Family
Vcc=2.50.2V Vcc=2.00.2V
All Family
-
0.4
V
Note 1 Commercial Product : TA=0 to 70C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : Vcc + 1.0V in case of pulse width 20ns 3. Undershoot : -1.0V in case of pulse width 20ns 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH
Test Conditions VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read
Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V
Min -1 -1 Read Write -
Typ 10 -
Max 1 1 2 3 15 351) 30 15
Unit A A mA mA
Vcc=3.3V@70ns Vcc=2.7V@120ns Vcc=2.2V@300ns 2.1mA at Vcc=3.0/3.3V
mA
Output low voltage
VOL
IOL
0.5mA at Vcc=2.5V 0.33mA at Vcc=2.0V -1.0mA at Vcc=3.0/3.3V
-
-
0.4
V
2.4 2.0 1.6 -
-
0.3 5
1)
Output high voltage
VOH
IOH
-0.5mA at Vcc=2.5V -0.44mA at Vcc=2.0V
V
Standby Current(TTL) Standby Current(CMOS)
ISB ISB1
CS1=VIH or CS2=VIL, Other inputs=VIL or VIH
CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V, Other inputs=0~Vcc
mA A
1.K6F1008V2M Family = 40mA 2. Super low power product = 1A with special handling.
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V 0.4 to 1.8V for Vcc=2.0V Input rising and falling time : 5ns Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V 1.1V for Vcc=2.5V 0.9V for Vcc=2.0V Output load (See right) :CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V for VCC=3.0/3.3V 2.3V for VCC=2.5V 1.8V for VCC=2.0V
AC CHARACTERISTICS(Commercial product :TA=0 to 70C, Industrial product : TA=-40 to 85C
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K6F1008V2M Family : Vcc=3.0~3.6V, K6F1008S2M Family : Vcc=2.3~3.3V, K6F1008R2M Family : Vcc=1.8~2.7V)
Speed Bins Parameter List Symbol 70ns 85ns 100ns 120ns 150ns 300ns Units
Min Max Min Max Min Max Min Max Min Max Min Max Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1, tCO2 tOE tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 70 10 5 0 0 10 70 65 0 65 55 0 0 30 0 5 70 70 35 25 25 25 85 10 5 0 0 15 85 70 0 70 60 0 0 35 0 5 85 85 45 25 25 25 100 10 5 0 0 15 100 80 0 80 70 0 0 40 0 5 100 100 50 30 30 30 120 10 5 0 0 15 120 100 0 100 80 0 0 50 0 5 120 120 60 35 35 35 150 20 10 0 0 15 150 120 0 120 100 0 0 60 0 5 150 150 75 40 40 40 300 50 30 0 0 30 300 300 0 300 200 0 0 120 0 20 300 300 150 60 60 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V
1)
Min 1.5 0 tRC
Typ -
Max 3.6 5.0 2) -
Unit V A ns
Vcc=3.0V, CS1Vcc-0.2V 1) See data retention waveform
1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or CS20.2V(CS2 controlled) 2. Super low power product = 1A with special handling.
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
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Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH tRC
OE tOLZ tLZ Data Valid tOHZ
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) tWR(4)
CMOS SRAM
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WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4)
CMOS SRAM
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WE
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 3.0/2.7/2.3/1.8V tSDR Data Retention Mode tRDR
2.2V VDR CS1VCC-0.2V
CS1 GND
CS2 controlled
VCC 3.0/2.7/2.3/1.8V CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND CS20.2V
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PACKAGE DIMENSIONS
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeter(inch)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
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#1 20.87 MAX 0.822 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004
( 0.71 ) 0.028
0.41
0.016 -0.002
1.27 0.050
0.05 0.002 MIN
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Revision 3.0 July 1998
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
CMOS SRAM
Units: millimeter(inch)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.000.20 0.7870.008 #32 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#1
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0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047 MAX
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
0.10 MAX 0.004
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40 0.20 0.528 0.008 #32
#1
( 8.40 0.331 MAX 8.00 0.315
0.25 ) 0.010
0.50 0.0197
#16
#17 1.00 0.10 0.039 0.004
0.25 TYP 0.010
11.80 0.10 0.465 0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 MIN 1.20 0.047 MAX
0~8
0.45~0.75 0.018~0.030
(
0.50 ) 0.020
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Revision 3.0 July 1998
0.10 MAX 0.004 MAX
K6F1008V2M, K6F1008S2M, K6F1008R2M Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
Top View B 6 A C/2 B Ball #A1 C D E F G H B1 5 4 Bottom View B 3 2
CMOS SRAM
Units: millimeter(inch)
Ball #A1
1
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B/2
SRAM Die
B/2
Elastomer Side View Detail A D 0.25/Typ. A Y Detail A
0.55/Typ.
C
0.32/Typ.
C1 Elastomer Die 0.3/Typ. Notes. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) Revision 3.0 July 1998
Min A B B1 C C1 D E E1 E2 Y 5.90 7.90 0.30 -
Typ 0.75 6.00 3.75 8.00 5.25 0.35 0.80 0.55 0.25 -
Max 6.10 8.10 0.40 0.81 0.08
C
11
C
C/2
E2
E
E1

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